Senior Analog Design Engineer

Company Description 1-VIA develops innovative high-speed optical and electrical CMOS retimers and linear drive optics products that support ultra-low-power, low-latency interconnects for data centers in the era of AI, large-scale and exascale computing. Its patented silicon Transimpedance Amplifier (TIA), Laser Driver (LD), PAM-X DSP ASICs, and linear drive optics solutions enable cloud and service providers to deliver significantly higher data performance with reduced power consumption. The company’s architectures are designed from the ground up to address next-generation networking and computing demands. 1-VIA’s engineering and management teams combine deep experience in optical systems, networking and advanced mixed-signal design, including ADC, DAC, DSP, LD, PLL, SerDes, TIA and algorithm development, making it a leader in high-speed interconnect technology.

Role Description The Senior Analog Design Engineer role at 1-VIA is a full-time, on-site position based in Reading. This role focuses on designing, simulating, and verifying high-performance analog and mixed-signal blocks for optical and electrical high-speed products, including TIAs, LDOs, and power management circuits. Responsibilities include developing transistor-level circuit architectures, running simulations (corner, Monte Carlo, noise, linearity, and transient analyses), and collaborating closely with layout engineers to ensure robust, manufacturable designs. The engineer will participate in design reviews, contribute to IP and block-level specifications, and support lab bring-up, characterization, and debug of silicon. The role also involves working cross-functionally with digital, system, and product engineering teams to ensure designs meet performance, power, area, and reliability targets for data center and AI applications.

Qualifications

• Strong expertise in analog and mixed-signal IC design for high-speed Ethernet SerDes applications, including transmitter (TX), receiver (RX), CDR, PLL/DLL, equalization, and clock distribution circuits.
• Demonstrated experience in transistor-level circuit design and implementation using industry-standard EDA tools such as Cadence Virtuoso, Spectre, HSPICE, or equivalent tools.
• Strong knowledge of high-speed analog design techniques including low-jitter clocking, low-noise design, signal integrity, channel equalization (CTLE/DFE/FFE), termination schemes, and power-efficient architectures for multi-gigabit Ethernet links.
• Experience with Ethernet SerDes standards and architectures, including IEEE Ethernet PHY specifications for 10G/25G/50G/100G/200G/400G interfaces and protocols such as KR, CR, SR, and PAM4 signaling.
• Proficiency in simulation, modeling, and verification of analog and mixed-signal blocks, including transient, AC, noise, jitter, corner, Monte Carlo, EM/IR, and reliability analyses.
• Experience designing high-speed building blocks such as PLLs, LC/VCOs, CDRs, serializers/deserializers, bias circuits, bandgap references, LDOs, high-speed comparators, samplers, and clock/data paths.
• Strong understanding of power management and supply integrity techniques for high-speed SerDes systems, including on-chip regulation, decoupling strategies, substrate noise isolation, and supply noise mitigation.
• Hands-on experience with silicon bring-up and validation using lab equipment such as high-bandwidth oscilloscopes, BERTs, VNAs, spectrum analyzers, and automated measurement/debug setups.
• Familiarity with layout-dependent effects and analog layout considerations, including matching, shielding, parasitic extraction, electromigration, ESD, and high-speed routing constraints.
• Experience collaborating with digital, verification, package, SI/PI, and physical design teams for full-chip integration and successful tape-out.
• Bachelor’s degree in Electrical Engineering or a related field required; Master’s or PhD specializing in Analog/Mixed-Signal IC Design, RFIC, or High-Speed SerDes design preferred.