Principal ASIC Design Verification Engineer – AI Accelerator / SoC

We are seeking an experienced Principal ASIC Design Verification Engineer to develop and execute comprehensive verification solutions for next-generation AI accelerators and high-performance SoC subsystems.

The ideal candidate will have strong hands-on experience in ASIC functional verification, with a solid understanding of GPU, NPU, or complex SoC subsystem architectures. The candidate should be proficient in verification planning, SystemVerilog/UVM testbench development, test case generation, and execution of comprehensive IP Verification Plans.

This position focuses on hands-on verification engineering, complex design debugging, functional coverage closure, and ensuring design correctness from specification through silicon tape-out.

We are looking for a highly skilled individual contributor who can independently develop robust verification environments, identify complex functional issues, and collaborate effectively with design engineers to deliver production-quality ASIC designs.

Responsibilities

1. ASIC Functional Verification

• Develop and execute comprehensive functional verification strategies for AI accelerators, GPU, NPU, and complex SoC subsystems.
• Analyze architecture and microarchitecture specifications to identify verification requirements, functional scenarios, corner cases, and potential design risks.
• Develop detailed IP Verification Plans (IVP), including coverage goals, test scenarios, and verification methodologies.
• Translate design specifications into executable verification plans, test cases, assertions, and coverage models.
• Perform block-level, subsystem-level, and SoC-level functional verification.
• Identify, debug, and resolve complex functional issues in collaboration with RTL design engineers.

2. Testbench Development and Verification Methodology

• Design, develop, and maintain reusable verification environments using SystemVerilog and UVM.
• Develop constrained-random and directed test cases to validate functional behavior, protocol compliance, and corner cases.
• Implement verification components, including drivers, monitors, agents, scoreboards, reference models, checkers, and functional coverage collectors.
• Develop transaction-level verification environments and reusable verification IP.
• Integrate behavioral models, reference models, and third-party verification IP into simulation environments.
• Develop assertions and protocol checkers to detect functional and interface violations.
• Improve verification efficiency through automation, regression management, and reusable testbench infrastructure.

3. Verification Planning and IVP Execution

• Create detailed verification plans based on architecture, microarchitecture, and functional specifications.
• Define verification scenarios, test cases, coverage points, and expected results for each functional feature.
• Establish traceability between design requirements, verification test cases, and functional coverage.
• Execute IP IVP through directed testing, constrained-random simulation, and coverage-driven verification.
• Develop and maintain automated regression suites and analyze regression results.
• Identify verification gaps and develop additional tests to achieve functional coverage closure.
• Analyze code coverage, functional coverage, assertion coverage, and verification completeness.
• Document verification results, outstanding issues, coverage reports, and sign-off status.

4. AI Accelerator and SoC Subsystem Verification

• Verify complex compute datapaths, control logic, memory subsystems, and data movement architectures used in AI accelerators.
• Develop verification scenarios for parallel processing engines, tensor computation units, scheduling logic, and accelerator control mechanisms.
• Verify memory access, DMA transactions, arbitration, buffering, flow control, and on-chip interconnect functionality.
• Validate subsystem-level interactions, including error handling, backpressure, reset sequences, and corner-case conditions.
• Develop end-to-end data integrity and transaction checking mechanisms across complex SoC subsystems.
• Collaborate with architecture and design engineers to understand functional requirements and identify potential architectural or microarchitectural issues.

6. Debugging, Regression, and Verification Closure

• Debug complex RTL and testbench issues using waveform analysis, simulation logs, assertions, and transaction-level debugging.
• Work with design engineers to isolate root causes of functional failures and validate RTL fixes.
• Develop scripts and automation tools for test execution, regression analysis, and reporting.
• Optimize simulation performance and verification efficiency for large-scale designs.
• Support verification sign-off through functional coverage closure, code coverage analysis, and resolution of critical defects.
• Participate in pre-silicon validation, FPGA prototyping, emulation, and post-silicon debugging as needed.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 10+ years of hands-on experience in digital ASIC/SoC functional verification.
• Strong architecture and microarchitecture understanding of at least one of the following: GPU or parallel computing architectures; NPU, AI accelerator, or machine learning processor architectures; Complex SoC subsystems, such as memory controllers, interconnect fabrics, DMA engines, or high-performance processing subsystems
• Extensive experience in SystemVerilog and UVM-based verification methodology.
• Proven experience developing reusable testbenches, verification components, scoreboards, reference models, and functional coverage models.
• Strong experience in verification plan generation, test case development, and IVP execution.
• Proficiency in constrained-random verification, directed testing, assertion-based verification, and coverage-driven verification.
• Solid understanding of digital logic, RTL design, state machines, pipelining, memory systems, and on-chip interconnect architectures.
• Experience in IP-level or SoC-level verification, including integration testing and system-level debugging.
• Familiarity with industry-standard simulation and debugging tools, such as Cadence Xcelium, Synopsys VCS, Siemens Questa, or equivalent.
• Experience with regression automation, functional coverage analysis, code coverage, and verification closure.
• Proficiency in scripting languages such as Python, Perl, Tcl, or shell scripting.
• Strong analytical, debugging, and problem-solving skills.
• Ability to independently develop and execute verification environments for complex ASIC functional blocks and subsystems.

Preferred Qualifications

• Direct verification experience with GPU, NPU, AI accelerator, or heterogeneous computing SoCs.
• Experience with chip-to-chip and die-to-die interconnect verification.
• Knowledge of LPDDR5/LPDDR5X, LPDDR6, and PCIe Gen5/Gen6, including protocol behavior, controller architecture, and verification methodologies.
• Experience with formal verification, including property checking, assertion-based formal verification, and formal verification tools.
• Familiarity with SystemVerilog Assertions (SVA) and formal property development.
• Experience with AMBA AXI/ACE/CHI, NoC architectures, cache coherency, and memory consistency verification.
• Experience with AI/ML accelerator workloads, including matrix multiplication, tensor operations, transformer models, and inference processing.
• Experience developing C/C++, Python, or MATLAB-based reference models and integrating them into SystemVerilog testbenches through DPI-C.
• Familiarity with hardware/software co-verification, embedded firmware, drivers, and system-level validation.
• Experience with FPGA prototyping, hardware emulation, or acceleration platforms.
• Familiarity with low-power verification, clock/reset verification, CDC/RDC verification, and power management scenarios.
• Experience with advanced semiconductor process technologies and complex SoC tape-out verification.