Design Verification Engineer
We are looking for experienced SoC Design Verification Engineers with 5–20 years of experience in semiconductor and SoC verification.
Key Skills Required
- Strong hands-on experience in SystemVerilog and UVM
- SoC / Subsystem-level Design Verification
- UVM Testbench Development, Reuse & Debugging
- Embedded C Test Development and Verification
- RTL Simulation Debugging
- Functional Coverage & Coverage Closure
- Regression Execution and Debugging
- ARM-based SoC Architecture
- Python / Perl / Shell Scripting
What We're Looking For
- Experience working on complex SoC designs.
- Strong debugging and problem-solving skills.
- Ability to enhance existing UVM verification environments.
- Experience with processor-based verification and large-scale regressions.