Senior SoC Design Verification Engineer

Key Skills: System Verilog, UVM, SoC Verification, C, Debugging, Functional Coverage, Gate level simulation

Role Overview

We are looking for experienced SoC Design Verification (DV) Engineers to work on the verification of a next-generation, multi-die System-on-Chip (SoC) design.

Engineers will be responsible for subsystem-level and SoC-level functional verification using System Verilog/UVM methodology, as well as processor-driven verification using C-based test programs executing on embedded processor cores.

The role requires strong debugging and analytical skills, an understanding of ARM processor based SoC architecture, and the ability to efficiently adapt existing verification environments to evolving design requirements.

Key Responsibilities-

1. Subsystem and SoC Functional Verification

2. System Verilog/UVM Testbench Reuse and Enhancement

3. Processor-Based C Test Development and Verification

4. Regression Execution, Debugging, and Coverage Closure

5. Verification Planning and Collaboration

Required Technical Skills

Essential Skills

• Strong hands-on experience in digital design verification using System Verilog and UVM.
• Experience working with existing UVM testbenches, including modifying, extending, and debugging reusable verification components.
• Good understanding of constrained-random verification, functional coverage, assertions, scoreboards, and checkers.
• Experience in subsystem-level or SoC-level functional verification.
• Strong understanding of SoC architectures, bus protocols, register interfaces, and processor-controlled peripherals.
• Experience developing, executing, or debugging embedded C tests for processor-based SoC verification.
• Ability to debug complex RTL simulation failures using industry-standard simulators and waveform debugging tools.
• Experience executing regressions, analyzing failures, and driving functional coverage closure.
• Working knowledge of scripting languages such as Python, Perl, or shell scripting.
• Familiarity with version control systems and verification development workflows.

Candidate Profile

The ideal candidate should

• Have strong practical experience in debugging and enhancing existing verification environments.
• Be comfortable understanding complex, previously developed UVM testbenches rather than relying exclusively on developing new environments from scratch.
• Demonstrate the ability to analyze design changes and identify required verification updates.
• Possess strong RTL debugging and problem-solving capabilities.
• Have experience working with large SoC verification regressions.
• Be capable of independently owning verification activities for assigned subsystems.
• Understand the relationship between UVM-based verification and processor-driven C test verification.

Educational Qualifications

Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, VLSI, or a related discipline.

Key Hiring Priorities

Candidates will be evaluated primarily on

1. System Verilog/UVM proficiency – Ability to understand, modify, and debug existing verification environments.
2. SoC/subsystem verification experience – Practical experience with complex RTL designs and subsystem interactions.
3. Debugging and problem-solving skills – Ability to independently investigate simulation failures and identify root causes.
4. Processor-based C verification – Experience developing or debugging C tests running on SoC processor cores.
5. Verification reuse and regression management – Ability to efficiently adapt existing testbenches and test suites to design changes.
6. Coverage and verification closure – Experience identifying verification gaps and achieving sign-off objectives.