SoC DV Engineer — UVM/SystemVerilog & Embedded C

DELTACLASS TECHNOLOGY SOLUTIONS LIMITED is seeking experienced SoC Design Verification Engineers to verify next-generation multi-die SoC designs. You will perform subsystem- and SoC-level functional verification using SystemVerilog/UVM, and develop processor-based C tests for embedded cores.

You will reuse and enhance existing UVM testbenches, debug complex RTL simulations, and drive regression and coverage closure with a disciplined verification plan and cross-functional collaboration.